Logic circuits such as Transistor Transistor Logic (TTL), Diode Transistor Logic (DTL), etc. are used in some cases near a device which generates a high voltage. For example, in case such logic circuits are used in the circuits connected to peripheral devices such as the CRT display device of a personal computer, a surge voltage of several hundreds to several tens of hundreds of volts is applied to the power supply line of a logic circuit in a moment when the power supply switch of the peripheral circuits is turned ON or OFF and thereby the transistors in the output stage of such logic circuits may be broken.
The process until occurrence of breakdown of transistors in the output stage of such logic circuit are explained with reference to a conventional 2-input NAND TTL circuit shown in FIG. 1. A multiemitter npn transistor T.sub.1 of the input stage in FIG. 1 has a base connected to a power supply line V.sub.cc through a resistor R.sub.1, a collector connected to the base of a phase splitter transistor T.sub.2 and two emitters to which respective input signals X.sub.1 and X.sub.2 are applied. Such phase splitter transistor T.sub.2 has a collector connected to the power supply line V.sub.cc through a resistor R.sub.5 and an emitter connected to the base of a pull-down transistor T.sub.3 of the output stage. The collector of phase splitter transistor T.sub.2 is connected to the base of a transistor T.sub.5, which has a collector connected to the power supply line V.sub.cc and an emitter connected to the base of a pull-up transistor T.sub.4 in the output stage. The collector of the pull-up transistor T.sub.4 is connected to the power supply line V.sub.cc. The emitter of the pull-down transistor T.sub. 3 is connected to a ground line GND. Both the emitter of the pull-up transistor T.sub.4 and the collector of the pull-down transistor T.sub.3 are connected to an output terminal OUTPUT. Such pull-up transistor T.sub.4 and transistor T.sub.5 form an off-buffer circuit which operates with fast switching speed by improving the rising characteristic when the pull-down transistor T.sub.3 is cut-off, namely the potential of output terminal OUTPUT changes to a high (H) level from a low (L) level with its output impedance kept lower. The base and emitter of the pull-up transistor T.sub.4 are connected through a resistor R.sub.3 to turn OFF the transistor T.sub.4 by discharging the base thereof and to make faster the falling characteristic of the potential at the output terminal OUTPUT more rapid when transistor T.sub.4 is cut-off. The base of pull-down transistor T.sub.3 and the ground line GND are connected through a resistor R.sub.4 to discharge the base of transistor T.sub.3 and make the rising characteristic of the potential at the output terminal OUTPUT more rapid. A resistor R.sub.2 is connected between the power supply line V.sub.cc and the base of phase splitter transistor T.sub.2. This resistor R.sub.2 supplied a base current to the transistor T.sub.2 and this resistor R.sub.2 is not always required. It should be noted that the transistors T.sub.2, T.sub.3 and T.sub.5 are Schottky barrier diode clamp transistors for preventing their excessive saturation.
The TTL circuit of FIG. 1 provides a NAND function which makes the potential of the output terminal OUTPUT L level only when both input signals X.sub.1 and X.sub.2 become H level. When both input signals X.sub.1 and X.sub.2 are H level, a base-to-collector junction of the transistor T.sub.1 is forward-biased, a current flows from the power supply line V.sub.cc through the resistor R.sub.1 and the current becomes a base current of the phase splitter transistor T.sub.2 with a current flowing through the resistor R.sub.2. In this case, the phase splitter transistor T.sub.2 in ON, a current is supplied to the collector of transistor T.sub.2 through a resistor R.sub.5, such current becomes a collector current and the emitter current of such transistor T.sub.2 flows into the base of pull-down transistor T.sub.3 and the resistor R.sub.4. When the pull-down transistor T.sub.3 is ON, since a potential of connecting point N.sub.1 of the collector phase splitter transistor T.sub.2 and the resistor R.sub.5 is L level, both the transistor T.sub.5 and the pull-up transistor T.sub.4 are OFF so that the potential of output terminal OUTPUT becomes L level.
Here, when a high voltage is applied to the power supply line V.sub.cc, a base current and a collector current of the transistor T.sub.2 and also a base current and an emitter current of the transistor T.sub.3 increase. Therefore the voltages between the collector and emitter of the transistor T.sub.2 and between the base and emitter of the transistor T.sub.3 increase due to internal resistance of the transistor T.sub.2 and transistor T.sub.3, so that a potential of the connecting point N.sub.1 of the transistor T.sub.2 and the resistor R.sub.5 increases. Consequently, both transistors T.sub.5 and T.sub.4 are turned ON. Therefore, since both the pull-down transistor T.sub.3 and pull-up transistor T.sub.4 in the output stage are turned ON, an excessive current I flows to the ground line GND from the power supply line V.sub.cc through the transistors T.sub.3, T.sub.4 in the output stage and thereby these transistors T.sub.3, T.sub.4 are destroyed.
That is, the base-emitter junction of the transistors is broken by a penetration of aluminum which is formed as an emitter electrode.
Therefore, it is desirable that the pull-down transistor and the pull-up transistor in the output stage are protected from breakdown when a high voltage is applied to the power supply line.